计算机科学论文代写 User Interfaces Ic Compiler

计算机科学论文代写 User Interfaces Ic Compiler

5.9 Performing Prototype Global Routing

One can perform prototype global routing to get an estimate of the routability and congestion of the design. Global routing is done to detect possible congestion “hot spots” that might exist in the floorplan due to the placement of the hard macros or inadequate channel spacing.

To perform global routing, use the route_fp_proto command.

5.10 Performing Hierarchical Clock Planning

This section describes how to reduce timing closure iterations by performing hierarchical clock planning on a top-level design during the early stages of the virtual flat flow, after plan groups are created and before the hierarchy is committed. One can perform clock planning on a specified clock net or on all clock nets in the design.

• Setting Clock Planning Options:

To set clock planning options, use the set_fp_clock_plan_options command.

• Performing Clock Planning Operations:

To perform clock planning operations, use the compile_fp_clock_plan command.

• Generating Clock Tree Reports:

To generate clock tree reports, use the report_clock_tree command.

• Using Multivoltage Designs in Clock Planning:

Clock planning supports multivoltage designs. Designs in multivoltage domains operate at various voltages. Multivoltage domains are connected through level-shifter cells. A level-shifter cell is a special cell that can carry signals across different voltage areas.

• Performing Plan Group-Aware Clock Tree Synthesis in Clock Planning:

With this feature, clock tree synthesis can generate a clock tree that honors the plan groups while inserting buffers in the tree and prevent new clock buffers from being placed on top of a plan group unless they drive the entire subtree inside that particular plan group. This results in a minimum of clock feedthroughs, which makes the design easier to manage during partitioning and budgeting. [16]

5.11 Performing In-Place Optimization

In-place optimization is an iterative process that is based on virtual routing. Three types of optimizations are performed: timing improvement, area recovery, and fixing DRC violations. These optimizations preserve the netlist’s logical hierarchy as well as the physical locations of the cells.

To perform in-place optimization, use the optimize_fp_timing command.

5.12 Performing Routing-Based Pin Assignment

IC Compiler provides two ways to perform pin assignment: on soft macros (traditional pin assignment) or on plan groups (pin cutting flow).

To assign pin constraints, use the set_fp_pin_constraints command.

To assign soft macros pins, use the place_fp_pins command.

To perform Block Level Pin Assignmentuse, use the place_fp_pins -block_level command.

To align soft macro pins, use the align_fp_pins command.

To remove soft macro pin overlaps, use the remove_fp_pin_overlaps command.

5.13 Performing RC Extraction

Perform postroute RC estimation by using the extract_rc command.

5.14 Performing Timing Analysis

Use the report_timing command to generate timing reports for the design. Depending on the options selected, one can report valid paths for the entire design or for specific paths. The timing report helps evaluate why some parts of a design might not be optimized.

5.15 Performing Timing Budgeting

During the design planning stage, timing budgeting is an important step in achieving timing closure in a physically hierarchical design. The timing budgeting algorithm determines the corresponding timing boundary constraints for each top-level soft macro or plan group (block) in a design. If the timing boundary constraints for each block are met when they are implemented, the top-level timing constraints are satisfied.

Timing budgeting distributes positive and negative slack between blocks and then generates timing constraints in the Synopsys Design Constraints (SDC) format for block-level implementation.

To generate a pre-budgeting timing analysis report file, use the check_fp_timing_environment command.

To run the timing budgeter, use the allocate_fp_budgets command.

Immediately after budgeting a design, you can use the check_fp_budget_result command to perform post-budget analysis. [16]

5.16 Committing the Physical Hierarchy

This section describes how to commit the physical hierarchy after finalizing the floorplan by converting plan groups to soft macros. Committing the hierarchy creates a new level of physical hierarchy in the virtual flat design by creating CEL views for selected plan groups. After committing the physical hierarchy, you can also “uncommit” the physical hierarchy by converting the soft macros back into plan groups.

In addition, this section also describes how to propagate top-level preroutes into soft macros, recover all pushed-down objects in child cells to the top-level, and uncommit the physical hierarchy by converting soft macros back into plan groups.

To convert plan groups to soft macros, use the commit_fp_plan_groups command.

To push down physical objects to the soft macro level, use the push_down_fp_objects command.

To push up physical objects to the soft macro level, use the push_up_fp_objects command.

To uncommit the physical hierarchy, use the uncommit_fp_soft_macros command. [16]

5.17 Refining the Pin Assignment

One can analyze and evaluate the quality of the pin assignment results by checking the

placement of soft macros pins in the design and the pin alignment.

To check the placement of soft macro pins, use the check_fp_pin_assignment command.

To check the pin alignment, use the check_fp_pin_alignment command. [16]