计算机科学论文代写 User Interfaces Ic Compiler

计算机科学论文代写 User Interfaces Ic Compiler

IC Compiler is the software package from Synopsys for Physical Design of ASIC. It provides necessary tools to complete the back end design of the very deep submicron designs. The inputs to the IC Compiler are: a gate-level netlist which can be from DC Compiler or third-party tools, a detailed floorplan which can be from previous Design Planning through IC Compiler or other third-party tools, timing constraints and other constraints, physical and timing libraries provided by manufacturer, and foundry-process data. IC Compiler generates a GDSII-format file as output ready for tape out of the chip. In addition, it is possible to export a Design Exchange Format (DEF) file of placed netlist data ready for a third-party router. IC Compiler uses a binary Synopsys Milkyway database, which can be used by other Synopsys tools based on Milkyway. [16]

4.2 User Interfaces

IC Compiler can be used either with Shell interface (icc_shell) or with Graphical user interface (GUI). Shell interface is the command-line interface, which is used for batch mode, scripts, typing commands, and push-button type of operations. Graphical user interface (GUI) is an advanced graphical analysis and physical editing tool. Certain tasks, such as very accurately displaying the design and providing visual analysis tools, can only performed from the GUI. Also tool command language (Tcl), which is used in many applications in the EDA industry, is available to IC Compiler. Using Tcl, you can write reusable procedures and scripts.

The IC Compiler design flow is an easy-to-use, single-pass flow that provides convergent timing closure. Figure 4.1 shows the basic IC Compiler design flow, which is centered around three core commands that perform placement and optimization (place_opt), clock tree synthesis and optimization (clock_opt), and routing and postroute optimization (route_opt). [16]

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